Gate-level logic simulation is used extensively to verify the correctness of design netlists for integrated circuits. Typically, input stimuli are applied to the netlist, and the simulation results are compared with a golden model or pre-defined checkers. However, when unknown values (Xs) exist, gate-level simulation can no longer produce correct results due to a condition known as X-pessimism, in which simulation Xs are propagated even though the digital logic 0/1 value can be known.
Reference is now made to FIG. 1, showing a schematic diagram of an exemplary design netlist 100 in which X-pessimism occurs, according to an illustrative embodiment. As shown in FIG. 1, the output 110 of gate g6 should be 0 but logic simulation produces an X value instead. Such inaccuracy can, in turn, produce numerous false Xs during simulation, rendering gate-level simulation highly inaccurate, or even useless in some instances. This problem is becoming more severe due to physical optimizations and low-power requirements that allow Xs to exist in the design.
One prior art solution to the problem is to deposit random values at registers, such as the work by Hira et al., in U.S. Published Patent Application No. 2010/0017187, entitled RANDOM INITIALIZATION OF LATCHES IN AN INTEGRATED CIRCUIT DESIGN. The Hira approach eliminates X problems by converting Xs into non-X values. However, each deposited value only represents one of the two possible values that the register can have. This can disadvantageously cause bugs to escape verification.
Reference is now made, by way of example, to FIG. 2 showing a schematic diagram of an exemplary integrated circuit design netlist in which random initialization of registers can cause missed bugs. Assume that it is a bug in the circuit of FIG. 2 if reg3 latches at 1 at the first cycle. This bug may be missed according to the prior art Hira approach which deposits random values to reg1 and reg2 unless the deposited values are 1 for both registers.
To overcome the X-pessimism problems in gate-level simulation, it is desirable to locate false Xs that are produced during simulation. Reference is made, by way of example, to Chang et al., “Handling Nondeterminism in Logic Simulation So That Your Waveform Can Be Trusted Again”, IEEE D&T Early Access, which proposes a formal technique and process that locates false Xs during simulation. However, this solution is not generic. More particularly, the proposed solution replaces the false Xs in registers with the correct non-X values when the formal analysis is applied during simulation. Accordingly, this solves the problem of false Xs produced during simulation at the time, but does not resolve any subsequent false Xs that may occur, even if the conditions that produced the false Xs are identical.
It is desirable to provide systems, methods and processes for correcting gate-level simulation when unknown values (Xs) exist.